1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
For power saving of semiconductor devices such as processors, it is effective to vary voltage to be applied in a multi-step manner depending on process load burdened on the processors or the like. More specifically, it is effective to vary threshold voltage value of gate electrodes of transistors, by applying a voltage (back bias) to a region where the transistors are formed in the semiconductor devices, to thereby control voltage to be applied to the region where the transistors are formed.
In some cases, the semiconductor devices such as processors have a plurality of regions differing from each other in the functions thereof, and this raises a demand of controlling the threshold voltage value of the gate electrodes of the transistors for every region. Also in this case, it is effective to apply the voltage (back bias) to every specific region in the semiconductor devices so as to control the voltage to be applied to the regions having the transistors formed therein, to thereby vary the threshold voltage value of the gate electrodes of the transistors.
One known example of conventional semiconductors allowing application of the back bias is disclosed, for example, in Japanese Laid-Open Patent Publication No. 2-283062. According to this literature, a reverse-conductivity-type well region is provided to an one-conductivity-type semiconductor substrate, one-conductivity-type field effect transistors are formed in the reverse-conductivity-type well region, and reverse-conductivity-type field effect transistors are formed on the substrate. The literature also describes a configuration in which the reverse-conductivity-type well region is provided so as to close the circumferences of the surficial region of the substrate having the reverse-conductivity-type field effect transistor formed therein. In other words, an N-type well “ocean” is formed in a P-type substrate, and P-type region “islands” are formed in the N-type well “ocean”.
Japanese Laid-Open Patent Publication No. 2-283062 also describes that this configuration makes it possible to dispense with well-to-well interconnections, and to achieve downsizing and higher density of CMOS ICs.
There is also known another conventional semiconductor device as described in Japanese Laid-Open Patent Publication No. 7-58289.
FIG. 7 is a sectional view showing a configuration of the semiconductor device. A semiconductor substrate 3 has two deep N-wells 5a and 5b formed therein by diffusing an N-type impurity to a large depth. The deep N-well 5a further has a P-well 6a and an N-well 7a formed therein, to thereby form a CMOS digital circuit (not shown). The N-well 7a is connected with a digital power source VDD via a high-concentration impurity diffused layer N+. The deep N-well 5b further has a P well 6b and N-well 7b formed therein, to thereby form a CMOS analog circuit (not shown). The N-well 7b is connected with an analog power source VDD via a high-concentration impurity diffused layer N+.
A P-well 4 is formed in a surficial region of the semiconductor substrate 3 between the digital circuit area and the analog circuit area, and two N-type, high-concentration impurity diffused layers N+ and a single P-type high-concentration impurity diffused layer P+ are formed in the P-well layer 4. One of two impurity-diffused regions N+ is connected to the digital power source VDD, and the other is connected to the analog power source VDD. The impurity-diffused layer P+ is connected to the ground power source (not shown) via a substrate dedicated grounding electrode, so that the P-well 4 serves as a grounding region.
Japanese Laid-Open Patent Publication No. 7-58289 describes that, this configuration is characterized by a triple well structure in which each of the regions respectively having the digital circuit and the analog circuit formed therein has the deep N-well, and that this structure electrically isolates both circuits from each other, to thereby suppress electrical interference between the digital circuit and the analog circuit.
The prior arts described in the above literatures, however, still have some room for improvement in the points below.
First, the semiconductor device described in Japanese Laid-Open Patent Publication No. 2-283062 tends to increase the resistivity of the region of the N-type well arranged between the P-type wells, because the region of the N-type well arranged between the P-type wells has an only a small width of the N-type region. This is highly causative of degradation of operation characteristics of PMOS transistors when the PMOS transistors are formed in the region of the N-well surrounded by the P-well.
Second, the semiconductor device described in Japanese Laid-Open Patent Publication No. 7-58289, having the plurality of N-well “islands” in the P-type “ocean” makes it difficult to control well potential of such plurality of N-type wells en bloc. This consequently makes it difficult to collectively control threshold voltage values of the gate electrodes of the PMOS transistors. Any possible efforts of collectively controlling the potential of the plurality of N-type wells will demand a plurality of additional metal interconnections laid between the plurality of N-wells, and will complicate the interconnection layout and increase the chip area.
The present invention was conceived after considering the above-described situations, and is to stably provide a high-quality semiconductor device allowing collective control of the threshold voltage values of gate electrodes of transistors which reside in one-conductivity-type regions and of transistors which reside in a reverse-conductivity-type region.